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A Dynamically Reconfigurable RF NoC for Many-Core

Abstract : With the growing number of cores on chips, conventional electrical interconnects reach scalability limits, leading the way for alternatives like Radio Frequency (RF), optical and 3D. Due to the variability of applications, communication needs change over time and across regions of the chip. To address these issues, a dynamically reconfigurable Network on Chip (NoC) is proposed. It uses RF and Orthogonal Frequency Division Multiple Access (OFDMA) to create communication channels whose allocation allows dynamic recon-figuration. We describe the NoC architecture and the distributed mechanism of dynamic allocation. We study the feasibility of the NoC based on state of the art components and analyze its performances. Static analysis shows that, for point to point communications, its latency is comparable with a 256-node electrical mesh and becomes lower for wider networks. A major feature of this architecture is its broadcast capacity. The RF NoC becomes faster with 32 nodes, achieving a ×3 speedup with 1024. Under realistic traffic models, its dynamic reconfigurability provides up to ×6 lower latency while ensuring fairness.
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Contributor : Alexandre Brière <>
Submitted on : Tuesday, June 23, 2015 - 2:27:33 PM
Last modification on : Friday, July 10, 2020 - 4:00:57 PM
Document(s) archivé(s) le : Tuesday, April 25, 2017 - 7:14:23 PM


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Alexandre Brière, Eren Unlu, Julien Denoulet, Andrea Pinna, Bertrand Granado, et al.. A Dynamically Reconfigurable RF NoC for Many-Core. ACM Great Lakes Symposium on VLSI, May 2015, Pittsburgh, United States. pp.139-144, ⟨10.1145/2742060.2742082⟩. ⟨hal-01166859⟩



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