Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs

M. Dubois (1) , Haralampos-G Stratigopoulos (2) , Salvador Mir (2) , Manuel J. Barragan (2)

1 UPMF IUG - Université Pierre Mendès France - Grenoble 2 - Institut d'urbanisme de Grenoble
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

Validation of an embedded test technique in terms of its expected yield loss and test escape metrics is a key step before it can be deployed in high-volume manufacturing. However, performing this validation at the design stage usually demands extensive computational resources, which may render electrical simulations infeasible. In this paper, we propose a digital test technique for dynamic test of ΣΔ ADCs based on a digital ternary stimulus together with an advanced simulation framework for its validation. The proposed simulation strategy relies on a combination of transistor-level simulations, behavioural simulations, and statistical tools. To show the feasibility of our approach, we use the proposed validation framework to compare the ternary stimulus with a digital bitstream stimulus, as well as with a standard high-resolution analog sine-wave stimulus.

Mots clés: circuits....; Embedded System Testing; testing

Domaines: Micro et nanotechnologies/Microélectronique

M. Dubois, Haralampos-G Stratigopoulos, Salvador Mir, Manuel J. Barragan. Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs. IFIP/IEEE 22nd International Conference on Very Large Scale Integration (VLSI-SoC'14), Oct 2014, Playa del Carmen, Mexico, Mexico. pp.1-6, ⟨10.1109/VLSI-SoC.2014.7004153⟩. ⟨hal-01118108⟩