Automated Generation of Instruction Set Simulator from Specification

Vania Joloboff (1) , Shengpeng Liu (2) , Fei He (2)

1 TEMPO - Trustworthy EMbedded PlatfOrms
2 THU - Tsinghua University [Beijing]

We present here an architecture compiler, namely a software that takes as input the description of a processor architecture as it is available from the vendors on their web site, and generates an instruction set simulator for that processor, which can be readily integrated into a simulation framework. This architecture compiler extracts relevant information from the .pdf file, translated into an XML specification. After further XML transformations, the C++ code of the simulator is finally generated. The paper details the approach and the results for the ARM Version 7 processor, that is suitable for other architectures as well.

Mots clés: Compiler; Hardware Simulation; Computer Architecture; Instruction Set Simulator

Domaines: Architectures Matérielles [cs.AR]; Modélisation et simulation

Vania Joloboff, Shengpeng Liu, Fei He. Automated Generation of Instruction Set Simulator from Specification. International Conference on Computer Engineering (ICOCE 2014), Prof. Yulin Wang, Wuhan University, China Prof. Yulin Wang, Wuhan University, China and Prof. Sheng-Uei Guan, Xi'an Jiaotong-Liverpool University, China, Nov 2014, Shenzhen, China. ⟨hal-01081105⟩