A very low power CMOS 28FDSOI programmable fractional frequency divider for Wifi-WiGig

Abstract : A 2.4 GHz very low-power programmable fractional frequency divider is presented in this work. A new kind of pulse swallowing architecture is exposed, offering news possibilities in terms of frequency range, frequency step and power consumption. This circuit was designed and implemented in 28nm FDSOI CMOS from STMicroelectronics. The divider consumes 300 μA over 1 V.
Document type :
Conference papers
Complete list of metadatas

https://hal.archives-ouvertes.fr/hal-01070746
Contributor : Equipe Conception de Circuits <>
Submitted on : Thursday, October 2, 2014 - 11:24:19 AM
Last modification on : Wednesday, October 9, 2019 - 9:30:27 PM

Identifiers

  • HAL Id : hal-01070746, version 1

Citation

Mathieu Vallet, Olivier Richard, Yann Deval, Didier Belot. A very low power CMOS 28FDSOI programmable fractional frequency divider for Wifi-WiGig. IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S conf 2014), Oct 2014, San Fransisco, United States. pp.62-65. ⟨hal-01070746⟩

Share

Metrics

Record views

164