A 97mW 0-4GHz 65nm CMOS Concurrent Receiver - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2014

A 97mW 0-4GHz 65nm CMOS Concurrent Receiver

Résumé

Telecommunication industry claims for an increase of data rate. Techniques must sustain this effort especially by achieving several Gpbs transceivers consumming a very low power. A Sampled Analog Signal Processor was developed performing a Fast Fourier transform using voltage samples to challenge this idea. It receives any RF signal from 0 to 5 GHz, whatever the band and modulation schemes. The circuit was designed in 65nm CMOS technology and demonstrates the feasibility of a concurrent reception within a frequency of 0 to 4GHz at a power consumption of 97mW.

Domaines

Electronique
Fichier non déposé

Dates et versions

hal-01064363 , version 1 (16-09-2014)

Identifiants

  • HAL Id : hal-01064363 , version 1

Citer

Francois Rivet, Yann Deval. A 97mW 0-4GHz 65nm CMOS Concurrent Receiver. ICSICT 2014, Oct 2014, GUILIN, China. pp.25-31. ⟨hal-01064363⟩
53 Consultations
0 Téléchargements

Partager

Gmail Facebook X LinkedIn More