FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation

Abstract : In this paper, we present an FPGA modelling of a distributed and synchronized clock generation for different clock domains based on coupled all-digital phase locked loops (ADPLLs). An implementation of a programmable and reconfigurable 10 ×10 ADPLL network is described, designed for prototyping distributed clock generation in large synchronous system on chip (SoC). The paper emphasizes the reconfigurability of proposed system, which allows exploiting stability issues and nonlinear behavior of a N × M network of coupled oscillators (the dimension can be configured from 1 × 1 to 10 × 10). Configurations with different parameters are compared and analyzed. A dynamic setup mechanism is proposed, allowing selecting the desired synchronized state. Experimental results validate theoretical analysis about circuit parameters and demonstrate the global synchronization of network and performance for different configurations.
Document type :
Conference papers
Complete list of metadatas

Cited literature [8 references]  Display  Hide  Download

https://hal.sorbonne-universite.fr/hal-01053762
Contributor : Chuan Shan <>
Submitted on : Monday, August 4, 2014 - 6:25:40 PM
Last modification on : Wednesday, May 15, 2019 - 3:39:03 AM
Long-term archiving on : Tuesday, November 25, 2014 - 11:22:06 PM

File

bare_conf_v5.pdf
Files produced by the author(s)

Identifiers

Citation

Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, et al.. FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation. Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on, Dec 2013, Cancun, Mexico. pp.1 - 6, ⟨10.1109/ReConFig.2013.6732295⟩. ⟨hal-01053762⟩

Share

Metrics

Record views

556

Files downloads

442