On-chip clock error characterization for clock distribution system

Chuan Shan 1 Dimitri Galayko 1 François Anceau 1
1 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : In this paper, we investigate a test strategy for characterization of clock error statistics between two clock domains in high-speed clocking systems (gigahertz and more). The method allows an indirect measurement (not based on time interval measurement) of clock error distribution by observing the integrity of a periodic sequence transmitted between two clocking domains. The method is compatible with fully on-chip implementation, and the readout of result to off-chip signals is cadenced at low rate. The strategy aims at picoseconds resolution without complex calibration. The idea was first validated by a discrete prototype at downscaled frequencies, and then a high frequency on-chip prototype was designed using 65 nm CMOS technology. Simulation results predict a measurement precision of less than ±2.5 ps. The article presents the theory, exposes the hardware implementation, and reports the experimental validation and simulation results of two prototypes.
Type de document :
Communication dans un congrès
VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on, Aug 2013, Natal, Brazil. pp.102-108, 2013, 〈10.1109/ISVLSI.2013.6654630〉
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Dernière modification le : vendredi 31 août 2018 - 09:25:55
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Chuan Shan, Dimitri Galayko, François Anceau. On-chip clock error characterization for clock distribution system. VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on, Aug 2013, Natal, Brazil. pp.102-108, 2013, 〈10.1109/ISVLSI.2013.6654630〉. 〈hal-01053759〉

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