FPGA implementation of reconfigurable ADPLL network for distributed clock generation

Abstract : This paper presents an FPGA platform for the design and study of network of coupled All-Digital Phase Locked Loops (ADPLLs), destined for clock generation in large synchronous System on Chip (SoC). An implementation of a programmable and reconfigurable 4×4 ADPLL network is described. The paper emphasizes the difference between the FPGA and ASIC-based implementation of such a system, in particular, implementation of digitally controlled oscillators and phase-frequency detector. The FPGA-implemented network allows studying complex phenomena related to coupled ADPLL operation and exploiting stability issues and nonlinear behavior. A dynamic setup mechanism has been proposed for the network, allowing selecting the desirable synchronized state. Experimental results demonstrate the global synchronization of network and performance of the network for different configurations.
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Communication dans un congrès
FTP 2011 - International Conference on Field Programmable Technology, Dec 2011, New Delhi, India. IEEE, pp.1-4, 2011, 〈10.1109/FPT.2011.6132670〉
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Dernière modification le : jeudi 3 mai 2018 - 15:18:05
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Chuan Shan, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, et al.. FPGA implementation of reconfigurable ADPLL network for distributed clock generation. FTP 2011 - International Conference on Field Programmable Technology, Dec 2011, New Delhi, India. IEEE, pp.1-4, 2011, 〈10.1109/FPT.2011.6132670〉. 〈hal-01053755〉

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