Analysis and optimization of a novel high voltage striped STI-LDMOS transistor on SOI CMOS technology

Gaëtan Toulon (1) , Ignacio Cortes (2) , Frédéric Morancho (2) , Abdelhakim Bourennane (2) , Karine Isoird (1)

1 LAAS-ISGE - Équipe Intégration de Systèmes de Gestion de l'Énergie
2 LAAS - Laboratoire d'analyse et d'architecture des systèmes

This paper analyses the static and dynamic characteristics of a novel n-type lateral-double-diffused MOS (LDMOS) with a striped Shallow Trench Isolation (STI) structure - called Striped STI-LDMOS - for switching applications in the 100-150 voltage range by means of 3D TCAD numerical simulations. The proposed structure based on a 0.18μm SOI CMOS technology and defined with STI strips and gate field plate fingers located on top of the defined STI, exhibits much lower gate-to-drain (CGD) capacitances and gate charge (Qg) and a better electrical safe operating area (SOA) as compared with a conventional STILDMOS counterpart.

Mots clés: LDMOS transistor; Shallow Trench Isolation; safe operating area; gate-to-drain capacitance; SOI; TCAD simulations

Domaines: Micro et nanotechnologies/Microélectronique

Gaëtan Toulon, Ignacio Cortes, Frédéric Morancho, Abdelhakim Bourennane, Karine Isoird. Analysis and optimization of a novel high voltage striped STI-LDMOS transistor on SOI CMOS technology. International Seminar on Power Semiconductors (ISPS 2012), Aug 2012, Pragues, Czech Republic. pp.122-128. ⟨hal-01004508⟩