PowerCheck : an architectural-level power estimation tool

Matthieu Denoual (1) , David Saillé (2) , Olivier Sentieys (3)

1 Equipe Electronique - Laboratoire GREYC - UMR6072
2 LASTI - Laboratoire d'Analyse des Systèmes de Traitement de l'Information
3 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources

With the emergence of embedded processing systems, the power dissipation of very large scale integrated circuits is becoming a critical concern. Therefore power requirements are driving a new breed of computer-aided design tools. This paper addresses the problem of modeling power dissipation at a high level of abstraction. A modeling approach is presented that captures the dependence of the circuit modules power dissipation on theirs activities. We also introduce our RT level estimation tool, PowerCheck,partoftheBSS framework Breizh Synthesis System, PowerCheck takes place after the RTsynthesis, then it pro by the architecture and its use. The major interest of our approachisthatwe takeinto account the signal properties in our power dissipation estimates of complete architecture.

Mots clés: Power dissipation; High-level estimation; Signal properties

Domaines: Electronique

Matthieu Denoual, David Saillé, Olivier Sentieys. PowerCheck : an architectural-level power estimation tool. Workshop on Multi-Architecture Low-Power Design (MALOPD), 1999, Moscou, Russia. pp 1-9. ⟨hal-00986443⟩