Verification and Validation of Meta-Model Based Transformation from SysML to VHDL-AMS

Jean-Marie Gauthier (1) , Fabrice Bouquet (1) , Ahmed Hammad (1) , Fabien Peureux (1)

1 FEMTO-ST - Franche-Comté Électronique Mécanique, Thermique et Optique - Sciences et Technologies (UMR 6174)

This paper proposes an approach to verify SysML models consistency and to validate the transformation of SysML models to VHDL-AMS code. This approach is based on two main solutions: the use of model-to-model transformation to verify SysML models consistency and writing unit tests to validate model transformations. The translation of SysML models into VHDL-AMS simulable code uses MMT (Model to Model Transformation) ATL Atlas Transformation Language and M2T (Model To Text) Acceleo tooling. The test validation of the model transformations is performed using EUNIT framework.

Domaines: Génie logiciel [cs.SE]

Jean-Marie Gauthier, Fabrice Bouquet, Ahmed Hammad, Fabien Peureux. Verification and Validation of Meta-Model Based Transformation from SysML to VHDL-AMS. MODELSWARD 2013, 1st Int. Conf. on Model-Driven Engineering and Software Development, Jan 2013, Spain. pp.123 - 128. ⟨hal-00935093⟩