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New reconfigurable fault tolerant FPGA architecture: A design for mission critical applications

Chagun Basha Basheer Ahmed 1 Sébastien Pillement 1, * Loïc Lagadec 2
* Corresponding author
2 Lab-STICC_ENSTAB_CACS_MOCS ; IDM
STIC - Pôle STIC [Brest], Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : Reconfigurable field programmable gate arrays (FPGAs) are employed extensively in many application domains due to their flexibility, high-density functionality and performance. However, the challenge that must be tackled during system design is their high susceptibility to the radiation-induced faults and the physical defects in the circuit due to presence (variability) or appearance (aging). In general, current FPGAs are not designed to work under these error prone environments, except for specific circuits that have been radiation-hardened at the fabrication process level, but at a very high cost overhead, which makes them less interesting from an economic point of view. These issues can be handled by involving proper fault mitigation mechanisms at different levels of FPGA architecture. We then plan to develop a low-cost reliable FPGA with supporting EDA tool-suite that offers a complete environment for a fault tolerant system design. This article presents the proposed ARDyT FPGA architecture. The additional features introduced in this architecture ensures the reliability and increased flexibility in the design.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-00921552
Contributor : Sandrine Charlier <>
Submitted on : Friday, December 20, 2013 - 3:40:40 PM
Last modification on : Monday, November 30, 2020 - 7:22:06 PM

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  • HAL Id : hal-00921552, version 1

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Chagun Basha Basheer Ahmed, Sébastien Pillement, Loïc Lagadec. New reconfigurable fault tolerant FPGA architecture: A design for mission critical applications. Workshop on Reconfigurable Computing (WRC), Jan 2014, Vienne, Austria. pp.WRC 2014. ⟨hal-00921552⟩

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