Evaluation of delay PUFs on CMOS 65nm technology: ASIC vs FPGA

Zouha Cherif (1, 2) , Jean-Luc Danger (2) , Florent Lozac'H (2) , Yves Mathieu (3) , Lilian Bossuet (1)

1 LHC - Laboratoire Hubert Curien
2 Télécom ParisTech
3 LTCI - Laboratoire Traitement et Communication de l'Information

This paper presents a comparative study of delay Physically Unclonable Functions (PUFs) designed in CMOS-65nm technology platforms: ASIC and FPGA (Xilinx Virtex-5). The performances are analyzed for two types of silicon PUFs, namely the arbiter and the loop PUFs. For this purpose, a PUF has been speci cally designed, the \mixed PUF", to allow a fair comparison between the two structures. The principle of the mixed PUF design consists on the use of the same delay chains for both PUFs. The analysis is based on PUF responses obtained at di erent operating conditions for 18 ASICs. Each one embeds 49 PUF instances. The comparison analysis reveals that overall the arbiter PUF structure has the worst performance when compared to the loop PUF, on both platforms.

Mots clés: PUF; randomness; steadiness; uniqueness; FPGA; ASIC

Domaines: Electronique

Zouha Cherif, Jean-Luc Danger, Florent Lozac'H, Yves Mathieu, Lilian Bossuet. Evaluation of delay PUFs on CMOS 65nm technology: ASIC vs FPGA. International Workshop on Hardware and Architectural Support for Security and Privacy, HASP 2013, Jun 2013, Tel-Aviv, Israel. pp.Article n° 4. ⟨hal-00859079⟩