Fast and accurate behavioural simulation of fractional-N frequency synthesizer for the optimization of the lock time
Résumé
Today, the current need consisting of implementing more and more complex systems imply the implementation of new methodologies to make the CAD product reliable in order to improve time to market, study costs, reusability and reliability of the design process. This paper proposes a high level design approach applied for the simulation and the optimization of fractional-N synthesizer acting as a direct GPSK modulator and designed for the UMTS standard application. It uses the hardware description language VHDL-AMS and a genetic algorithm to optimize the modulator with a considerably reduced CPU time.