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Sequential Multiplier with Sub-linear Gate Complexity

Anwar Hasan 1 Christophe Negre 2, 3
2 DALI - Digits, Architectures et Logiciels Informatiques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, UPVD - Université de Perpignan Via Domitia
Abstract : In this article, we present a new sequential multiplier for extended binary finite fields. Like its existing counterparts, the proposed multiplier has a linear complexity in flip-flop or temporary storage requirements, but a sub-linear complexity in gate counts. For the underlying polynomial multiplication, the proposed field multiplier relies on the Horner scheme.
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https://hal.archives-ouvertes.fr/hal-00813843
Contributor : Christophe Negre <>
Submitted on : Tuesday, April 16, 2013 - 11:18:47 AM
Last modification on : Thursday, May 24, 2018 - 3:59:23 PM

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Anwar Hasan, Christophe Negre. Sequential Multiplier with Sub-linear Gate Complexity. Journal of Cryptographic Engineering, Springer, 2012, 2 (2), pp.91-97. ⟨10.1007/s13389-012-0035-1⟩. ⟨hal-00813843⟩

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