Sequential Multiplier with Sub-linear Gate Complexity

Anwar Hasan (1) , Christophe Negre (2, 3)

1 ECE - Department of Electrical and Computer Engineering [Waterloo]
2 DALI - Digits, Architectures et Logiciels Informatiques
3 UPVD - Université de Perpignan Via Domitia

In this article, we present a new sequential multiplier for extended binary finite fields. Like its existing counterparts, the proposed multiplier has a linear complexity in flip-flop or temporary storage requirements, but a sub-linear complexity in gate counts. For the underlying polynomial multiplication, the proposed field multiplier relies on the Horner scheme.

Mots clés: sub-linear gate complexity; Binary polynomial multiplication; sequential multiplier; Horner scheme; sub-linear gate complexity.

Domaines: Cryptographie et sécurité [cs.CR]

Anwar Hasan, Christophe Negre. Sequential Multiplier with Sub-linear Gate Complexity. Journal of Cryptographic Engineering, 2012, 2 (2), pp.91-97. ⟨10.1007/s13389-012-0035-1⟩. ⟨hal-00813843⟩