Statistical leakage estimation in 32nm CMOS considering cells correlations

Abstract : In this paper a method to estimate the leakage power consumption of CMOS digital circuits taking into account input states and process variations is proposed. The statistical leakage estimation is based on a pre-characterization of library cells considering correlations (ρ) between cells leakages. A method to create cells leakage correlation matrix is introduced. The maximum relative error achieved in the correlation matrix is 0.4% with respect to the correlations obtained by Monte Carlo simulations. Next the total circuit leakage is calculated from this matrix and cells leakage means and variances. The accuracy and efficiency of the approach is demonstrated on a C3540 (8 bit ALU) ISCAS85 Benchmark circuit.
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Communication dans un congrès
FTFC - 11th IEEE conference on Faible Tension Faible Consommation, Jun 2012, Paris, France. IEEE, pp.1-4, 2012, 〈10.1109/FTFC.2012.6231721〉
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Dernière modification le : jeudi 11 janvier 2018 - 01:48:43
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Smriti Joshi, Anne Lombardot, Marc Belleville, Edith Beigne, Stephane Girard. Statistical leakage estimation in 32nm CMOS considering cells correlations. FTFC - 11th IEEE conference on Faible Tension Faible Consommation, Jun 2012, Paris, France. IEEE, pp.1-4, 2012, 〈10.1109/FTFC.2012.6231721〉. 〈hal-00803441〉

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