Hardware Acceleration of SVM-Based Traffic Classification on FPGA

Tristan Groleat 1, 2 Matthieu Arzel 3, 4 Sandrine Vaton 1, 2
2 REOP - Réseaux d'opérateurs
IRISA-D2 - RÉSEAUX, TÉLÉCOMMUNICATION ET SERVICES, Télécom Bretagne
4 Lab-STICC_TB_CACS_IAS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : Understanding the composition of the Internet traffic has many applications nowadays, mainly tracking bandwidth consuming applications, QoS-based traffic engineering and lawful interception of illegal traffic. Although many classification methods such as Support Vector Machines (SVM) have demonstrated their accuracy, not enough attention has been paid to the practical implementation of lightweight classifiers. In this paper, we consider the design of a real-time SVM classifier at many Gbps to allow online detection of categories of applications. Our solution is based on the design of a hardware accelerated SVM classifier on a FPGA board.
Document type :
Conference papers
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https://hal.archives-ouvertes.fr/hal-00797503
Contributor : Bibliothèque Télécom Bretagne <>
Submitted on : Wednesday, March 6, 2013 - 3:30:31 PM
Last modification on : Thursday, October 17, 2019 - 12:36:49 PM

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  • HAL Id : hal-00797503, version 1

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Tristan Groleat, Matthieu Arzel, Sandrine Vaton. Hardware Acceleration of SVM-Based Traffic Classification on FPGA. IWCMC TRAC: International Wireless Communications and Mobile Computing Conference, International Workshop on TRaffic Analysis and Classification, Aug 2012, Limassol, Cyprus. ⟨hal-00797503⟩

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