Fast Integration of Hardware Accelerators for Dynamically Reconfigurable Architecture
Résumé
Dynamic reconfiguration of hardware resources is increasingly used in applications as a way to increase performances, resources integration or energy efficiency. As this evolution induces a change of the application execution paradigm, various tools have been set up to develop and manage these applications. But most do not allow direct re-use of legacy code, needing adaptation to match the provided environment. Moreover, partial reconfiguration is only at its early stages, and lacks easy ways of handling. We propose a design methodology and a runtime environment bringing fast integration of legacy hardware accelerators for partial and dynamic reconfigurable hardware architectures. Thanks to it, applications making use of dynamic hardware can be run directly on an Embedded Linux without noticing the reconfiguration flow. Moreover, our design methodology allows providing various implementations of a computation kernel, including both hardware and software ones. The implementation can then be chosen at execution time depending on available resources. In this article, we introduce the generic IP interface description making the re-use process possible. Furthermore, we present the results of a sample application running on our platform using software and hardware implementations. For hardware implementations, we obtain reconfiguration overhead as low as 0.16\% of the total kernel execution time.
Mots clés
Computer architecture
Hardware
IP networks
Kernel
Registers
Standards
Co-design methodologies
Design reuse
Interface design
Reconfigurable architectures
Runtime reconfiguration
total kernel execution time
legacy hardware accelerators
legacy code
hardware resources
hardware implementations
Linux
electronic engineering computing
embedded systems
logic circuits
logic design
dynamic reconfigurable hardware architectures
embedded Linux
energy efficiency
execution paradigm
generic IP interface description
partial reconfigurable hardware architectures
partial reconfiguration
software implementations
static hard-wired IP blocks
static hard-wired intellectual property blocks
Origine : Fichiers produits par l'(les) auteur(s)
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