Adaptive Stackable 3D Cache Architecture for Manycores

Eric Guthmuller (1) , Ivan Miro-Panades (1) , Alain Greiner (2)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 ALSOC - Architecture et Logiciels pour Systèmes Embarqués sur Puce

With the emergence of manycore architectures, the need of on-chip memories such as caches grows faster than the number of cores. Moreover the bandwidth to off-chip memories is saturating. Big memory caches can alleviate the pressure to off-chip accesses. In this paper, we present an adaptive 3D cache architecture taking advantage of dense vertical connections in stacked chips. Then we propose a dynamically adaptive mechanism to optimize the use of the aforementioned 3D cache architecture according to the workload needs. Finally, we analyze the gain on memory accesses and on software execution time in a realistic model of manycore architecture and we study the hardware cost of our proposal, showing that our approach can lead to a 50% reduction of both external memory accesses and application execution time.

Domaines: Micro et nanotechnologies/Microélectronique; Architectures Matérielles [cs.AR]

Eric Guthmuller, Ivan Miro-Panades, Alain Greiner. Adaptive Stackable 3D Cache Architecture for Manycores. VLSI (ISVLSI), 2012 IEEE Computer Society Annual Symposium on, Aug 2012, Amherst, MA, United States. pp.39-44, ⟨10.1109/ISVLSI.2012.36⟩. ⟨hal-00743530⟩