Failure modes and robustness of SiC JFET transistors under current limiting operations

Mounira Berkani (1) , Stéphane Lefebvre (1) , Othman Dhouha (1) , Moumen Sabrine (1, 2) , Zoubir Khatir (3) , Salah Tarek Ben (4)

1 SATIE - Systèmes et Applications des Technologies de l'Information et de l'Energie
2 IFSTTAR/LTN - Laboratoire des Technologies Nouvelles
3 INRETS/LTN - Laboratoire des Technologies Nouvelles
4 UTM - Université de Tunis El Manar

The paper presents results of ageing tests of normally-on SiC JFET prototype transistors from SiCED subjected to repetitive short circuit modes corresponding to current limitation operations. Experimental tests are detailed and the evolution during tests of ageing indicators like on-state resistance and saturation current are discussed. Finally, thermal simulation results are presented in order to understand and explain evolutions of some ageing indicators.

Mots clés: "Silicon Carbide )"; " Current limiter "; " JFET"; " Power semiconductor"; "Short circuit"; "Robustness".; Silicon Carbide ); Current limiter; JFET; Power semiconductor; Short circuit; Robustness

Domaines: Energie électrique

Mounira Berkani, Stéphane Lefebvre, Othman Dhouha, Moumen Sabrine, Zoubir Khatir, et al.. Failure modes and robustness of SiC JFET transistors under current limiting operations. Power Electronics and Applications (EPE 2011),, Aug 2011, Birmingham, United Kingdom. pp.1-10. ⟨hal-00713076⟩