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A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation

Abstract : This paper presents a CMOS 1.1-2.8 GHz 10 bits digitally controlled oscillator (DCO) for high speed clocking of SoCs. The DCO includes only 269 tuning cells, which is possible thanks to an original algorithm based on weighted combined thermometer code, used for the DCO frequency control. The control circuit of the DCO includes only binary-to-thermometer decoders: that was possible with the proposed technique of virtual extension of number of the DCO ring. It was implemented in 65- nm CMOS technology, with semi-custom layout design allowed to optimize the area on silicon. The design was validated by transistor-level ELDO extracted schematic simulation. Oscillator shows a good linearity in the frequency tunning range, with average power consumption 6mW/GHz with 1.1V supply voltage. Typical phase noise with 1MHz offset and 2GHz carrying frequency is -86.12dBc/Hz.
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https://hal.archives-ouvertes.fr/hal-00683074
Contributor : Eldar Zianbetov <>
Submitted on : Tuesday, March 27, 2012 - 4:35:15 PM
Last modification on : Monday, April 6, 2020 - 9:22:31 AM

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Eldar Zianbetov, François Anceau, Mohammad Javidan, Dimitri Galayko, Eric Colinet, et al.. A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation. ISCAS 2011 - IEEE International Symposium on Circuits and Systems, May 2011, Rio de Janeiro, Brazil. pp.2845-2848, ⟨10.1109/ISCAS.2011.5938198⟩. ⟨hal-00683074⟩

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