40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications

F. Abouzeid (1, 2) , S. Clerc (1) , F. Firmin (1) , Marc Renaudin (3) , G. Sicard (2)

1 STMicroelectronics
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
3 Tiempo Secure [Montbonnot Saint Martin]

Ultra-low voltage is now a well-known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. At 0.33V, it performs at 600 kHz with a dynamic energy consumption reduced by a factor 14x from nominal 1.1V. Based on this design, experiments, and preliminary silicon results, two additional libraries were developed in order to enhance future ultra-low voltage circuit performance.

Mots clés: CMOS; Low-power

Domaines: Micro et nanotechnologies/Microélectronique

F. Abouzeid, S. Clerc, F. Firmin, Marc Renaudin, G. Sicard. 40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications. ACM Transactions on Design Automation of Electronic Systems, 2011, 16 (3), pp.article 35. ⟨10.1145/1970353.1970369⟩. ⟨hal-00672355⟩