All-digital PLL array provides reliable distributed clock for SOCs

Mohammad Javidan (1) , Eldar Zianbetov (1) , François Anceau (1) , Dimitri Galayko (1) , Anton Korniienko (2, 3) , Eric Colinet (2) , Gérard Scorletti (3) , Jean-Michel Akre (4) , Jérome Juillard (4)

1 CIAN - Circuits Intégrés Numériques et Analogiques
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 MIS - Ampère, Département Méthodes pour l'Ingénierie des Systèmes
4 E3S - Supélec Sciences des Systèmes

This brief addresses the problem of clock generation and distribution in globally synchronous locally synchronous chips. A novel architecture of clock generation based on network of coupled all-digital PLLs is proposed. Solutions are proposed to overcome the issues of stability and undesirable synchronized modes (modelocks) of high-order bidirectional PLL networks. The VLSI implementation of the network is discussed in CMOS65 nm technology and the simulation results prove the reliability of the global synchronization by the proposed method.

Mots clés: high-order bidirectional PLL network; VLSI implementation; size 65 nm; clock distribution; all-digital PLL array; CMOS technology; clock generation; SOC; distributed clock reliability; globally synchronous locally synchronous chip

Domaines: Micro et nanotechnologies/Microélectronique; Automatique / Robotique

Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Anton Korniienko, et al.. All-digital PLL array provides reliable distributed clock for SOCs. 2011 IEEE International Symposium of Circuits and Systems (ISCAS), May 2011, Rio de Janeiro, Brazil. pp.2589-2592, ⟨10.1109/ISCAS.2011.5938134⟩. ⟨hal-00655799⟩