An Asynchronous FIR Filter Architecture coupled to a Level-Crossing ADC

T. Beyrouthy (1) , Laurent Fesquet (1) , M. Greitans (2) , R. Shavelis (2) , R. Robin (3)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
2 IECS - Institute of Electronics and Computer Science
3 CIME - Centre Interuniversitaire de Micro-Electronique

This paper presents the architecture of an asynchronous digital signal processing chain, working with non-uniformly sampled data in time. We focus on a Finite Impulse Response filter (FIR) applied to this non-uniform sampled signal obtained from an asynchronous analog to digital converter (A-ADC). The main advantage of combining the asynchronous design with the non-uniform sampling is the drastic reduction of the power consumption, thanks to the reduction of the computational load.

Mots clés: asynchronous circuits and systems

Domaines: Micro et nanotechnologies/Microélectronique

T. Beyrouthy, Laurent Fesquet, M. Greitans, R. Shavelis, R. Robin. An Asynchronous FIR Filter Architecture coupled to a Level-Crossing ADC. 9th International Conference on Sampling Theory and Applications (SampTA'11), May 2011, Singapore, Singapore. pp.Fr2S12.2 - P0190. ⟨hal-00646262⟩