A 2GHz CMOS DCO with optimized architecture for high speed clocking

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https://hal-supelec.archives-ouvertes.fr/hal-00631096
Contributor : Karine El Rassi <>
Submitted on : Tuesday, October 11, 2011 - 2:44:49 PM
Last modification on : Wednesday, May 15, 2019 - 3:39:15 AM

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  • HAL Id : hal-00631096, version 1

Citation

Eldar Zianbetov, Mohammad Javidan, François Anceau, Dimitri Galayko, Eric Colinet, et al.. A 2GHz CMOS DCO with optimized architecture for high speed clocking. International Symposium on Circuits and Systems (ISCAS'11), May 2011, Rio de Janeiro, Brazil. pp.2845-2848. ⟨hal-00631096⟩

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