From Mono-FPGA to Multi-FPGA Emulation Platform for NOC Performance Evaluations
Résumé
Experimental approaches used for architecture exploration and validation are often based on configurable logic device such as Field Programmable Gate Array (FPGA). System on Chip (SoC) and Network on Chip (NoC) architectures require multi-FPGA platforms as the resources of a single FPGA may not be big enough. Partitionning a NoC on a multi-FPGA platform requires special techniques for allocating communication channels, physical links and suitable resource allocation scheme. It is a time consuming process reducing the exploration space and validation. In this paper, we present a scalable emulation platform and its associated design flow based on a multi FPGA approach that allows quick exploration, evaluation and comparison of a wide range of NoC solutions. The efficiency of our approach is illustrated through the deployment of the Hermes NoC and its exploration on a mono FPGA and multi-FPGA platform with several traffic implementations.