Modeling of Time in Discrete-Event Simulation of Systems-on-Chip

Abstract : Today's consumer electronics industry uses modeling and simulation to cope with the complexity and time-to-market challenges of designing high-tech devices. In such context, Transaction-Level Modeling (TLM) is a widely spread modeling approach often used in conjunction with the IEEE standard SystemC discrete-event simulator. In this paper, we present a novel approach to modeling time that distinguishes between instantaneous actions and tasks with a duration. We argue that this distinction should be natural to the user. In addition, we show that it gives us important insight and better comprehension of what actions can overlap in time. We are able to exploit this distinction to parallelize the simulation, achieving an important speedup and exposing subtle software bugs related to parallelism. We propose a set of primitives and discuss the design decisions, expressiveness and semantics in depth. We present a research simulator called jTLM that implements all these ideas.
keyword : TLM time duration Java jTLM
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Communication dans un congrès
MEMOCODE, Jul 2011, Cambridge, United Kingdom. 2011
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Contributeur : Matthieu Moy <>
Soumis le : mercredi 25 mai 2011 - 11:22:50
Dernière modification le : lundi 21 mars 2016 - 17:31:10
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Giovanni Funchal, Matthieu Moy. Modeling of Time in Discrete-Event Simulation of Systems-on-Chip. MEMOCODE, Jul 2011, Cambridge, United Kingdom. 2011. 〈hal-00595637〉

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