An Approach Based on Edge Coloring of Tripartite Graph for Designing Parallel LDPC Interleaver Architecture

Sani Awais Hussein (1) , Philippe Coussy (2) , Cyrille Chavet (2) , Eric Martin (2)

1 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)
2 Lab-STICC_UBS_CACS_MOCS

A practical and feasible solution for LDPC decoder is to design partially-parallel hardware architecture. These architectures are efficient in terms of area, cost, flexibility and performances. However, this type of architecture is complex to design since concurrent read and write accesses to data have to be performed at each time instance without any conflict. To solve this memory mapping problem, we present in this paper, an original approach based on a tripartite graph modeling and a modified edge coloring algorithm to design parallel LDPC interleaver architecture.

Domaines: Algorithme et structure de données [cs.DS]; Traitement du signal et de l'image [eess.SP]; Traitement du signal et de l'image [eess.SP]; Architectures Matérielles [cs.AR]; Informatique et théorie des jeux [cs.GT]; Informatique et langage [cs.CL]; Systèmes embarqués

Sani Awais Hussein, Philippe Coussy, Cyrille Chavet, Eric Martin. An Approach Based on Edge Coloring of Tripartite Graph for Designing Parallel LDPC Interleaver Architecture. IEEE International Symposium on Circuits and Systems (ISCAS) 2011, May 2011, Rio de Janeiro, Brazil. pp.XX-YY. ⟨hal-00592617⟩