Turbo product code decoder without interleaving resource: From parallelism exploration to high efficiency architecture

Camille Leroux 1 Christophe Jego 2 Patrick Adde 1, 3 Deepak Gupta 1 Michel Jezequel 1, 3
3 Lab-STICC_TB_CACS_IAS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)
Abstract : This article proposes to explore parallelism in Turbo-Product Code (TPC) decoding through a parallelism level classification and characterization. From this design space exploration, an innovative TPC decoder architecture without any interleaving resource is presented. This architecture includes a fully-parallel SISO decoder capable of processing n symbols in one clock period. Syntheses results show the better efficiency of such an architecture compared with existing solutions. Considering a six-iteration turbo decoder of a BCH(32,26)2 product code, synthesized in 90 nm CMOS technology, 10 Gb/s can be achieved with an area of 600 Kgates. Moreover, a second architecture enhancing parallelism rate is described. The throughput is 50 Gb/s while an area estimation gives 2.2 Mgates. Finally, comparisons with existing TPC decoders and existing LDPC decoders are performed. They validate the potential of proposed TPC decoder for Gb/s optical fiber transmission systems.
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Camille Leroux, Christophe Jego, Patrick Adde, Deepak Gupta, Michel Jezequel. Turbo product code decoder without interleaving resource: From parallelism exploration to high efficiency architecture. Journal of Signal Processing Systems, Springer, 2011, 64 (1), pp.17-29. ⟨hal-00573278⟩

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