A SIMD Programmable Vision Chip with High Speed Focal Plane Image Processing

Abstract : A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators are implemented on the circuit. Each pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A 64×64 pixel proof-of-concept chip was fabricated in a 0.35 μm standard CMOS process, with a pixel size of 35 μm × 35 μm. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. The chip can capture raw images up to 10 000 frames per second and runs low-level image processing at a framerate of 2 000 to 5 000 frames per second.
Liste complète des métadonnées

Cited literature [51 references]  Display  Hide  Download

Contributor : Dominique Ginhac <>
Submitted on : Wednesday, September 15, 2010 - 10:45:00 PM
Last modification on : Tuesday, April 2, 2019 - 1:31:29 AM
Document(s) archivé(s) le : Friday, December 2, 2016 - 10:09:52 AM


Files produced by the author(s)




Dominique Ginhac, Jérôme Dubois, Michel Paindavoine, Barthélémy Heyrman. A SIMD Programmable Vision Chip with High Speed Focal Plane Image Processing. EURASIP Journal on Embedded Systems, SpringerOpen, 2009, pp.13. ⟨10.1155/2008/961315⟩. ⟨hal-00517911⟩



Record views


Files downloads