A high speed programmable focal-plane SIMD vision chip. Analog Integrated Circuits and Signal Processing

Abstract : A high speed analog VLSI image acquisition and low-level image processing system is presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Each pixel include a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A 64 × 64 pixel proof-of-concept chip was fabricated in a 0.35 μm standard CMOS process, with a pixel size of 35 μm × 35 μm. The chip can capture raw images up to 10,000 fps and runs low-level image processing at a framerate of 2,000–5,000 fps
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Dominique Ginhac, Jérôme Dubois, Barthélémy Heyrman, Michel Paindavoine. A high speed programmable focal-plane SIMD vision chip. Analog Integrated Circuits and Signal Processing. Analog Integrated Circuits and Signal Processing, Springer Verlag, 2010, 65 (3), pp.389-398. ⟨10.1007/s10470-009-9325-7⟩. ⟨hal-00482760⟩

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