Mixed-Signal Built-in Self-Calibrated Time-Interleaved ADC in 65nm CMOS Technology

Abstract : Analog-to-Digital (A/D) conversion is faced with strong requirements in terms of resolution and frequency. Time-Interleaved Analog-to-Digital Converters (TIADC) are popular because they offer a higher sampling frequency. But, their architecture introduces errors that affect the resolution of conversion. This paper presents a built-in method of calibration dedicated to TIADC. Mixed-simulations are performed merging transistor-level in 65nm CMOS technology and behavioral blocks in VHDL-AMS language to validate the feasibility of a Built-In Self-Calibration (BISC) system which corrects offset, gain and timing error. Technological constraints of the analog part of the BISC circuitry are highlighted. An orthogonal calibration is applied in a 4-ADC TIADC system and a detailed choice of the methodology is described
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Conference papers
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https://hal.archives-ouvertes.fr/hal-00476806
Contributor : Equipe Conception de Circuits <>
Submitted on : Tuesday, April 27, 2010 - 11:55:53 AM
Last modification on : Thursday, January 11, 2018 - 6:21:09 AM

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  • HAL Id : hal-00476806, version 1

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Francois Rivet, André Mariano, Dominique Dallet, Jean-Baptiste Begueret. Mixed-Signal Built-in Self-Calibrated Time-Interleaved ADC in 65nm CMOS Technology. NEWCAS 2010, Jun 2010, Canada. p250-251-252-253-254. ⟨hal-00476806⟩

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