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Conference papers

2-4 and 9-12 Gb/s CMOS Fully Integrated ILO-based CDR

Abstract : A CDR dedicated to satellite data link is presented. The clock recovery function is made-up of an Injection Locked Oscillator combined with an analog phase alignment circuit. The circuit covers two bit-rate ranges: 2.2 to 4.3 Gb/s and 9.1 to 12.1 Gb/s. It was designed in 130 nm CMOS bulk process from STMicroelectronics. The overall power dissipation is 400 mW in the first bit-rate range and 480 mW in the second including 220 mW for I/O buffers. The eye opening at 10e-9 of bit error rate is 940 mUI/440 mV at 3.1 Gb/s and 720 mUI/300 mV at 10.3 Gb/s.
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Contributor : Equipe Conception de Circuits <>
Submitted on : Thursday, March 25, 2010 - 2:49:52 PM
Last modification on : Wednesday, October 9, 2019 - 9:30:27 PM


  • HAL Id : hal-00466978, version 1


Olivier Mazouffre, Romaric Toupe, Michel Pignol, Yann Deval, Jean-Baptiste Begueret. 2-4 and 9-12 Gb/s CMOS Fully Integrated ILO-based CDR. 2010 IEEE Radio Frequency Integrated Circuits Symposium, May 2010, United States. p152-155. ⟨hal-00466978⟩



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