Multi-Core Code Generation From Interface Based Hierarchy

Jonathan Piat (1) , Shuvra S. Bhattacharyya (2) , Maxime Pelcat (3) , Mickaël Raulet (1)

1 IETR - Institut d'Electronique et de Télécommunications de Rennes
2 University of Maryland [College Park]
3 IETR - Institut d'Électronique et des Technologies du numéRique

Dataflow has proved to be an attractive computational model for programming digital signal processing (DSP) applications. A restricted version of dataflow, termed synchronous dataflow (SDF), offers strong compile-time predictability properties, but has limited expressive power. A new type of hierarchy semantics that we propose for the SDF model allows more expressivity in SDF while maintaining its predictability. This new hierarchy semantic is based on interfaces that fix the number of tokens consumed/produced by a hierarchical vertex in a manner that is independent or separate from the specified internal dataflow structure of the encapsulated subsystem. This interface-based hierarchy gives the application designer more flexibility to apply iterative design approaches, and to make optimizing choices at the design level. This type of hierarchy is also closer to the host language semantics (i.e., the the semantics of the languages, such as C, Java and Verilog/VHDL, in which the internal functionality of primitive SDF blocks is typically written) because hierarchy levels can be interpreted as code closures (i.e., semantic boundaries), and allow one to design iterative patterns. This paper presents our proposed approach to hierarchical SDF system design, and demonstrates how we can take advantage of the proposed hierarchy semantics to generate efficient static C code targeting embedded applications.

Domaines: Systèmes embarqués

Jonathan Piat, Shuvra S. Bhattacharyya, Maxime Pelcat, Mickaël Raulet. Multi-Core Code Generation From Interface Based Hierarchy. Conference on Design and Architectures for Signal and Image Processing (DASIP) 2009, Sep 2009, Sophia Antipolis, France. ⟨hal-00440479⟩