A Design Technique for Power Constrained CMOS Low-Noise Amplifier Dedicated to Wireless Sensor Networks

G. Terrasson (1) , R. Briand (1) , Skandar Basrour (2)

1 ESTIA INSTITUTE OF TECHNOLOGY
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

n wireless sensor network applications, autonomy is a critical feature. So, a new design method under power consumption constraint, dedicated to inductively degenerated Low-Noise Amplifier, is proposed in this article. A detailed analysis of power consumption, gain, noise and linearity performances of this topology is performed. The simulation results using MATLAB show the impact of each MOSFET dimensions into Low-Noise Amplifier performances. Based on these results, a new method to design Low-Noise Amplifier is proposed using an example. A 868-MHz Low-Noise Amplifier is then designed in CMOS 0.35 μm technology to validate our method. Considering the literature, measurement results show good characteristics: 13 dB gain, 1.5 dB Noise Figure with an ultra low-power consumption of 6.7 mW at supply voltage of 2 V.

Mots clés: wireless sensor network; CMOS

Domaines: Micro et nanotechnologies/Microélectronique

G. Terrasson, R. Briand, Skandar Basrour. A Design Technique for Power Constrained CMOS Low-Noise Amplifier Dedicated to Wireless Sensor Networks. Journal of Low Power Electronics, 2009, 5 (2), pp.196-205. ⟨10.1166/jolpe.2009.1020⟩. ⟨hal-00422325⟩