Direct mapping of sequential QDI controllers
Résumé
Asynchronous circuits have demonstrated their efficiency in many application fields such as low-power, low electro-magnetic emission, highly robust circuits, etc. Moreover, asynchronous circuits are quite natural for designing controllers. The design and the automation of asynchronous controllers has been an active field of research since many years. Today, very efficient tools are available. These tools generate different kind of asynchronous circuits: asynchronous burst mode state machines (minimalist and 3D tools), speed independent circuits (petrify and optimist tools). synchronous burst mode circuits are not so robust than QDI circuits – since they work with the fundamental mode assumption – and speed independent circuits are synthesized from a lower level graph description such as STG (State Transition Graph) than QDI circuits. These approaches are well-suited for designing small controllers but are inappropriate for complex circuits. In order to synthesize larger circuits, approaches based on hardware description languages have been developed. These methods target different types of circuits such as micro pipeline or QDI circuits. In this work, QDI circuits are especially interesting for controllers because they are close to those obtained with STG and particularly robust to PVT (Process, Voltage, and Temperature) thanks to a minimalist timing assumption. Whatever the delays in the interconnections and in the gates are, these circuits remain functional except in some specific “isochronic” forks. Therefore QDI controllers are well-suited to be used in advanced nanometric technologies such as 45 and 32 nm CMOS processes. The language-based approach is suitable for designing data path such as multipliers or adders, but it is not optimized for control dominant applications. The language-based model has been used to synthesize a controller with our tool (TAST). In the sequel, this controller is used as a reference to evaluate the improvement of our new method. This work – which aims to synthesize and optimize controllers using graphical model – proposes a direct mapping of controller using special communicating controllers called sequencers. The architecture of these components and the synthesis algorithm are described and explained in details. Two examples are introduced in order to make a comparison between our method and the one used in TAST. It also demonstrates the efficiency and advantages of our approach to other similar approaches. This evaluation has been done by electrical stimulation of circuits designed in 130 nm CMOS process from ST Microelectronics; the evaluated properties are peak currents, power, area and speed.