High-level symbolic simulation for automatic model extraction

F. Ouchet (1) , D. Borrione (1) , Katell Morin-Allory (1) , Laurence Pierre (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This paper describes VSYML, a symbolic simulator that extracts formal models from VHDL descriptions. The generated models are adequate to formal reasoning in various frameworks. VSYML is a reimplementation of its ancestor Theosim; it brings various improvements e.g., with regard to arrays and other complex data types.

Mots clés: simulation

Domaines: Micro et nanotechnologies/Microélectronique

F. Ouchet, D. Borrione, Katell Morin-Allory, Laurence Pierre. High-level symbolic simulation for automatic model extraction. IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS'09), Apr 2009, Liberec, Czech Republic. pp.218-221, ⟨10.1109/DDECS.2009.5012132⟩. ⟨hal-00417314⟩