On-chip interconnects energy consumption: High-level estimation and architectural optimizations

Antoine Courtay 1 Olivier Sentieys 2 Johann Laurent 3 Nathalie Julien 3
2 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
3 Lab-STICC_UBS_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
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https://hal.archives-ouvertes.fr/hal-00417253
Contributor : Antoine Courtay <>
Submitted on : Tuesday, September 15, 2009 - 2:54:00 PM
Last modification on : Wednesday, December 18, 2019 - 5:05:01 PM

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  • HAL Id : hal-00417253, version 1

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Antoine Courtay, Olivier Sentieys, Johann Laurent, Nathalie Julien. On-chip interconnects energy consumption: High-level estimation and architectural optimizations. 2009. ⟨hal-00417253⟩

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