On-chip interconnects energy consumption: High-level estimation and architectural optimizations

Antoine Courtay (1) , Olivier Sentieys (2) , Johann Laurent (3) , Nathalie Julien (3)

1 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)
2 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
3 Lab-STICC_UBS_CACS_MOCS

Mots clés: Interconnect; Power Consumption; Performance optimization

Domaines: Micro et nanotechnologies/Microélectronique

Antoine Courtay, Olivier Sentieys, Johann Laurent, Nathalie Julien. On-chip interconnects energy consumption: High-level estimation and architectural optimizations. 2009. ⟨hal-00417253⟩