Master Interface for On-Chip Hardware Accelerator Burst Communications

Antoine Fraboulet (1, 2) , Tanguy Risset (1, 2)

1 COMPSYS - Compilation and embedded computing systems
2 CITI - CITI Centre of Innovation in Telecommunications and Integration of services

We explain a systematic way of interfacing data-flow hardware accelerators (IP) for their integration in a system on chip. We abstract the communication behaviour of the data flow IP so as to provide basis for an interface generator. Then we measure the throughput obtained for different architectures of the interface mechanism by a cycle accurate bit accurate simulation of a SoC integrating a data-flow IP. We show in which configuration the optimal communication scheme can be reached.

Mots clés: system on chip; SoC; simulation; high level synthesis; interface generation

Domaines: Architectures Matérielles [cs.AR]

Antoine Fraboulet, Tanguy Risset. Master Interface for On-Chip Hardware Accelerator Burst Communications. The Journal of VLSI Signal, 2007, 49 (1), pp.73-85. ⟨10.1007/s11265-006-0045-2⟩. ⟨hal-00391222⟩