A Digitally Tuned Voltage Controlled Delay Element for 1-10GHz DLL-based Frequency Synthesis

Pierre-Olivier Lucas de Peslouan (1) , Cédric Majek (1) , Thierry Taris (1) , Yann Deval (1) , Didier Belot (2) , Jean-Baptiste Begueret (1)

1 IMS - Laboratoire de l'intégration, du matériau au système
2 ST-CROLLES - STMicroelectronics [Crolles]

This paper presents an original topology for Voltage Controlled Delay Element used in a DLL-based oscillator. This cell works from 1 to 10GHz achieving the phase noise performances required for the targeted wireless standards. The current consumption is lower than 9mA under 1V supply voltage. Thanks to the new topology a delay bank control scheme is feasible, paving the way to digitally controlled DLL.

Domaines: Electronique

Pierre-Olivier Lucas de Peslouan, Cédric Majek, Thierry Taris, Yann Deval, Didier Belot, et al.. A Digitally Tuned Voltage Controlled Delay Element for 1-10GHz DLL-based Frequency Synthesis. NEWCAS – TAISA'09, Jun 2009, Toulouse, France. pp.51-69. ⟨hal-00380884⟩