A CMOS Resizing Methodology for Analog Circuits: linear and non-linear applications

Abstract : This article proposes a CMOS resizing methodology for analog circuits during a technology migration. The scaling rules aim to be easy to apply and are based on the simplest MOS transistor model. This methodology represents a useful technique for resizing a design and may be used as a first-guess for an optimization procedure. The principle is to transpose one circuit topology from one technology to another, while keeping the main figures of merit, and the issue is to quickly calculate the new transistor dimensions. An optimization tool improves the results when it is necessary. This methodology is applied to both linear and non-linear examples: an OTA and a ring oscillator. The results are compared on four CMOS processes whose minimum length is respectively 0.8 m, 0.35 m, 0.25 m and 0.12 m
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IEEE Design & Test, IEEE, 2009, 26 (1), pp. 78-87, doi:10.1109
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Dernière modification le : jeudi 17 mai 2018 - 13:30:06

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Timothée Levi, Jean Tomas, Noëlle Lewis, Pascal Fouillat. A CMOS Resizing Methodology for Analog Circuits: linear and non-linear applications. IEEE Design & Test, IEEE, 2009, 26 (1), pp. 78-87, doi:10.1109. 〈hal-00359990〉

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