Speeding up behavioral test pattern generation using an algorithmicimprovement

Loic Vandevanter (1) , Jean-François Santucci (2) , Norbert Giambiasi (3)

1 EERIE
2 SPE - Sciences pour l'environnement
3 LSIS - Laboratoire des Sciences de l'Information et des Systèmes

n this paper, we focus on an improvement of test pattern generation for circuit descriptions written in hardware description languages according to their behavior. The improvement method stems from the “headlines” defined at the gate level by structural test approaches. The improvement method is implemented and inserted in a behavioral test pattern generator in order to be validated. Experimental results have been obtained which show the efficiency of our approach

Mots clés: Behavioral Testing; ATPG; Heuristic

Domaines: Modélisation et simulation; Micro et nanotechnologies/Microélectronique

Loic Vandevanter, Jean-François Santucci, Norbert Giambiasi. Speeding up behavioral test pattern generation using an algorithmicimprovement. 12th IEEE VLSI Test Symposium, 1994, Cherry Hill, NJ, United States. pp.226-231, ⟨10.1109/VTEST.1994.292308⟩. ⟨hal-00326750⟩