FPGA-based Architecture for Real-time Synaptic Plasticity Computation

Abstract : Synaptic plasticity provides the basis for most models of learning, memory and development in neural networks. The challenge for neuromorphic system designers is to find out efficient architectures to process accurately and speedily plasticity rules for a large number of synaptic connections. In this work, we propose a configurable architecture for real-time synaptic plasticity computation. Based on a dedicated plasticity processor, the architecture runs plasticity rules after a predefined configuration. As proof of concept, we implement on a commercial FPGA a biologically inspired form of spike timing-dependent plasticity (STDP) with complex time dependencies between pairs of pre- and post-synaptic spikes. Experimental results evaluate computation accuracy and speed as well as the number of synaptic connections we can process.
Type de document :
Communication dans un congrès
International Conference on Electronics, Circuits and Systems, (ICECS'08), Aug 2008, Malte, Malta. pp.93-96,, 2008
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https://hal.archives-ouvertes.fr/hal-00320751
Contributeur : Sylvain Saighi <>
Soumis le : jeudi 11 septembre 2008 - 15:50:51
Dernière modification le : jeudi 11 janvier 2018 - 06:21:06

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  • HAL Id : hal-00320751, version 1

Citation

B. Belhadj, J. Tomas, O. Malot, G. N'Kaoua, Y. Bornat, et al.. FPGA-based Architecture for Real-time Synaptic Plasticity Computation. International Conference on Electronics, Circuits and Systems, (ICECS'08), Aug 2008, Malte, Malta. pp.93-96,, 2008. 〈hal-00320751〉

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