Chapter "Formal Verification"

Abstract : This chapter is mostly an adaptation of the paper "LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level" to the context of the book written by my team in STMicroelectronics. It presents the toolchain LusSy and its application to formal verification of SystemC programs.
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Contributor : Matthieu Moy <>
Submitted on : Tuesday, August 12, 2008 - 1:35:19 PM
Last modification on : Monday, November 12, 2018 - 4:24:03 PM

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Matthieu Moy. Chapter "Formal Verification". Frank Ghenassia. Transaction-Level Modeling with SystemC. TLM Concepts and Applications for Embedded Systems, Springer, 15 p., 2005, ISBN: 0-387-26232-6. ⟨hal-00311014⟩

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