Nonidealities Study of a Continuous-Time Delta-Sigma Modulator Using VHDL-AMS Modeling

Abstract : In this paper, a complete high-speed Continuous-Time Bandpass Delta-Sigma modulator for digital receiver applications is modeled, using VHDL-AMS. The main Continuous-Time Delta-Sigma modulator's nonidealities such as excess loop delay, clock jitter and multi-bit feedback DAC element mismatch in the modulator loop are also modeled and their effects evaluated. An accurate understanding of these non-ideal phenomena allows to estimate the limits of the modulator and hence to design more robust building-blocks.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-00284755
Contributor : Equipe Conception de Circuits <>
Submitted on : Tuesday, June 3, 2008 - 4:14:11 PM
Last modification on : Wednesday, October 9, 2019 - 9:30:27 PM

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  • HAL Id : hal-00284755, version 1

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André Mariano, Dominique Dallet, Yann Deval, Jean-Baptiste Begueret. Nonidealities Study of a Continuous-Time Delta-Sigma Modulator Using VHDL-AMS Modeling. 13th Workshop on ADC Modelling and Testing, Sep 2008, Firenze, Italy. pp.25-28. ⟨hal-00284755⟩

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