Resizing methodology for CMOS analog circuit

Abstract : This paper proposes a CMOS resizing methodology for analog circuits during a technology migration. The scaling rules aim to be easy to apply and are based on the simplest MOS transistor model. The principle is to transpose one circuit topology from one technology to another, while keeping the main figures of merit, and the issue is to quickly calculate the new transistor dimensions. Furthermore, when the target technology has smaller minimum length, we expect to obtain a decrease of area. This methodology is applied to both linear and non-linear examples: an OTA and a ring oscillator. The results are compared on three CMOS processes whose minimum length is 0.8 µm, 0.35 µm, 0.25 µm.
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Timothée Levi, J. Tomas, N. Lewis, P. Fouillat. Resizing methodology for CMOS analog circuit. Proceedings SPIE VLSI Circuits and Systems III, May 2007, Maspalomas, Gran Canaria, Spain. pp.00. ⟨hal-00181420⟩

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