Temporal logic verification using simulation

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Conference papers
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https://hal.archives-ouvertes.fr/hal-00171560
Contributor : Brigitte Bidegaray-Fesquet <>
Submitted on : Wednesday, September 12, 2007 - 3:57:33 PM
Last modification on : Thursday, January 11, 2018 - 6:14:33 AM

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Georgios E. Fainekos, Antoine Girard, George J. Pappas. Temporal logic verification using simulation. Formal Modelling and Analysis of Timed Systems, FORMATS 2006, Sep 2006, Paris, France. pp.171-186. ⟨hal-00171560⟩

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