High Efficiency Protection Solution for Off-Chip Memory in Embedded Systems

Romain Vaslin (1) , Guy Gogniat (1) , Jean-Philippe Diguet (2) , Russell Tessier (3) , Wayne Burleson (3)

1 LESTER - Laboratoire d'Electronique des Systèmes TEmps Réel
2 Lab-STICC_UBS_CACS_MOCS
3 Department of Electrical and Computer Engineering [Amherst]

This paper proposes a complete hardware solution for embedded systems that fully protects off-chip memory. Our security core is based on one-time pad (OTP) encryption and a CRC32 integrity check module. These modules safeguard external memories for embedded processors against a series of well-known attacks, including replay attacks, spoofing attacks and relocation attacks. The implementation limits memory space overhead to about 18.75% and reduces memory latency from 14 cycles for a alternate approach to 3 clock cycles. A FPGA-based implementation of the security core has been completed to gauge the security overhead and to compare our approach with existing solutions.

Domaines: Cryptographie et sécurité [cs.CR]; Architectures Matérielles [cs.AR]; Systèmes embarqués

Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Wayne Burleson. High Efficiency Protection Solution for Off-Chip Memory in Embedded Systems. international conference on engineering of reconfigurable systems & algorithms, Jun 2007, Las Vegas, United States. pp.117. ⟨hal-00153120⟩