Optimal layout for 6H-SiC VJFET controlled current limiting device
Résumé
SiC-based devices are very suitable for high current and high voltage applications [H. Matsunami, Progress in wide bandgap semiconductor SiC for power devices, Invited Paper, ISPSD'00 22-25 May 2000, Toulouse]. Nevertheless, SiC material has some limitations that constrain the capability of these devices. This work is devoted to the design and fabrication of a new etched VJFET, which implements both gate and source in buried layers. This technological approach enables more flexibility in the basic cell layout design (square cells) than the conventional surface gate implementation. Therefore, various geometrical layouts have been investigated in order to find a trade-off between current density, driving ability and current limiting capability. The minimum lithography feature, reactive ion etching and the minimum spacing between adjacent implantations were key points in setting-up the design rules. I-V curves of the designed structures for a gate-to-source bias of 0 and -30 V has been performed at room temperature. All devices exhibit a current saturation at an on-state voltage higher than 10 V. The dependence of the internal access gate resistance on the layout has been checked by means of transconductance measurements. Transconductance has been estimated for each type of structure, being in the range of 57.8-672 mS/mm.. Nevertheless, a new figure of merit (the transconductance per active area) allows to find out the most suitable layout in terms of output current density and gate resistance. A comparison in terms of current and transconductance per source gives the best solution in terms of output saturation current and gate resistance. The results of those measurements are discussed with future perspectives for implementation of the most appropriated layout in an integrated system.