A FPGA Power Aware Design Flow

David Elleouet (1) , Yannig Savary (2) , Nathalie Julien (3)

1 IETR - Institut d'Electronique et de Télécommunications de Rennes
2 LESTER - Laboratoire d'Electronique des Systèmes TEmps Réel
3 Lab-STICC_UBS_CACS_MOCS

Today and tomorow, Electronic system design requires being concerned with the power issues. Currently usual design tools consider the application power consumption after RTL synthesis. We propose in this article a FPGA design flow wihich integrates the power consideration at the early stages. Thus, the designer determines quickly the algorithm and architecture adequacy wich respect thee design specification and the power budget.

Domaines: Traitement du signal et de l'image [eess.SP]; Architectures Matérielles [cs.AR]; Traitement du signal et de l'image [eess.SP]

David Elleouet, Yannig Savary, Nathalie Julien. A FPGA Power Aware Design Flow. Power and Timing Modeling, Optimization and Simulation 2006, Sep 2006, Montpellier, France. pp.XX-XX. ⟨hal-00105869⟩